Maxim - Ultra-High-Speed Flash Microcontroller User’s Guide.pdf

Dallas Semiconductor’s ultra-high-speed flash microcontroller is an 8051-compatible microcontroller that provides improved performance and power consumption when compared to the original 8051 version. It retains instruction set and object code compatibility with the 8051, yet performs the same operations in fewer clock cycles. Consequently, greater throughput is possible for the same crystal speed. As an alternative, the device can be run at a reduced frequency to save power. The more efficient design allows a much slower crystal speed to get the same results as an original 8051, using much less power.
The fundamental innovation of the ultra-high-speed flash microcontroller is the use of only one clock per instruction cycle compared with 12 for the original 8051. This results in up to 12 times improvement in performance over the original 8051 architecture and up to four times improvement over other Dallas Semiconductor high-speed microcontrollers. The device provides several peripherals and features in addition to all of the standard features of an 80C32. These include 16kB/32kB/64kB of on-chip flash memory, 1kB of on-chip RAM, four 8-bit I/O ports, three 16-bit timer/counters, two on-chip UARTs, dual data pointers, an on-chip watchdog timer, five levels of interrupt priority, and a crystal multiplier. The device provides 256 bytes of RAM for variables and stack; 128 bytes can be reached using direct or indirect addressing, or using indirect addressing only.
Table of Contents:

• SECTION 1: INTRODUCTION
• SECTION 2: ORDERING INFORMATION
• SECTION 3: ARCHITECTURE [ ALU ~ Special-Function Registers ~ Accumulator ~ B Register ~ Program Status Word ~ Data Pointer(s) ~ Stack Pointer ~ I/O Ports ~ Timer/Counters ~ UARTs ~ Scratchpad Registers (RAM) ~ Stack ~ Working Registers ~ Program Counter ~ Address/Data Bus ~ Watchdog Timer ~ Power Monitor ~ Interrupts ~ Timing Control ~ Flash Memory ]
• SECTION 4: PROGRAMMING MODEL [ Memory Organization ~ Memory Map ~ Register Map ~ Bit Addressable Locations ~ Working Registers ~ Stack ~ Address Modes ~ Program Status Flags ~ Special-Function Register Locations ~ Special-Function Registers ]
• SECTION 5: CPU TIMING [ Oscillator ~ XTAL1 ~ XTAL2 ~ Oscillator Characteristics ~ Crystal Selection ~ System Clock Divide Control ~ Instruction Timing ~ Nonpage Mode External Timing ~ Page Mode 1 External Timing—Pages 1:0 = 10b (Four Cycles) ~ Page Mode 1 External Timing—Pages 1:0 = 01b (Two Cycles) ~ Page Mode 1 External Timing—Pages 1:0 = 00b (One Cycle) ~ Page Mode 2 External Timing—Pages 1:0 = 11b ~ Comparison to the 8051 ]
• SECTION 6: MEMORY ACCESS [ Internal Flash Memory ~ ROMSize Feature ~ Flash Security Block/Lock Bits ~ Option Control Register Byte ~ Internal SRAM Memory ~ Program Memory Interface—Nonpage Mode ~ Program Memory Interface—Page Modes ~ Data Memory Interface ~ Nonpage Mode Data Memory Timing ~ Page Mode 1 Data Memory Timing—Pages 1:0 = 10b (Four Cycles) ~ Page Mode 1 Data Memory Timing—Pages 1:0 = 01b (Two Cycles) ~ Page Mode 1 Data Memory Timing—Pages 1:0 = 00b (One Cycle) ~ Page Mode 2 Data Memory Timing—Pages 1:0 = 11b (Four Cycles) ]
• SECTION 7: POWER MANAGEMENT [ Power Management Summary ~ Precision Voltage Monitor ~ Early-Warning Power-Fail Interrupt ~ Power-Fail Reset ~ Power-On Reset ~ Bandgap Select ~ Watchdog Wake-Up from Idle ~ Power Saving ~ Clock Divide Control ~ Idle Mode ~ Stop Mode ~ Ring Oscillator Wake-Up from Stop ~ Speed Reduction ~ Power Management Modes ~ Switchback ~ Clock Source Selection ~ Ring Oscillator Resume from Stop ]
• SECTION 8: RESET CONDITIONS [ Reset Sources ~ Power-On/Power-Fail Reset ~ Watchdog Timer Reset ~ Oscillator Fail-Detect Reset ~ Determining the Cause of a Reset ]
• SECTION 9: INTERRUPTS [ Interrupt Overview ~ Interrupt Sources ~ Interrupt Priorities ~ Interrupt Acknowledge Cycle ~ Interrupt Latency ]
• SECTION 10: I/O PORTS [ Parallel I/O ~ Port 0 ~ Port 2 ~ Port 1 ~ Port 3 ~ Alternate Functions of Ports 1 and 3 ~ Read-Modify-Write ~ Output Functions ~ Input Functions ]
• SECTION 11: PROGRAMMABLE TIMERS [ 16-Bit Timers ~ Timer 0, Timer 1 Modes ~ Mode 0 ~ Mode 1 ~ Mode 2 ~ Mode 3 ~ Timer 2 Modes ~ Watchdog Timer ]
• SECTION 12: SERIAL I/O [ Serial Mode Summary ~ Mode 0 ~ Mode 1 ~ Mode 2 ~ Mode 3 ~ Serial Port Initialization ~ Baud Rates ~ Serial I/O Description ~ Framing Error Detection ~ Multiprocessor Communication ]
• SECTION 13: TIMED-ACCESS PROTECTION [ Protected Bits ~ Protection Scheme ~ Valid Timed-Access Procedure ~ Invalid Timed-Access Procedure ~ Timed-Access Protects Watchdog ]
• SECTION 14: INSTRUCTION SET DETAILS
• SECTION 15: PROGRAM LOADING [ ROM Loader Mode ~ AutoBaud-Rate Detection ~ Command Line Interface ~ Command Line Syntax ~ Command Summaries ~ Error Messages ~ Parallel Programming Mode ~ User Code In-Application Programming Mode ~ Intel Hex File Format ]

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